1. Field of the Invention
The present invention relates generally to electronic packaging technology and, more particularly, to a method for forming chip stacks at the wafer level.
2. Description of the Related Art
In the package assembly process, a chip attaching process is used to attach a semiconductor chip, that has been separated from a wafer, to a substrate, such as a lead frame or a printed circuit board, for mechanical support and forming electrical interconnections. A typical chip attaching process includes applying an adhesive material to the substrate, separating the semiconductor chip from the wafer, transferring the semiconductor chip onto the adhesive material, and applying pressure and/or heat to the semiconductor chip to complete the attachment.
As packaging technology has advanced, multi-chip packages have been developed that can integrate several chips of the same or different types in a single package. A three-dimensional chip stack package has been developed as one type of multi-chip package. In a typical the chip stack package, a lower chip is attached to the substrate and an upper chip is attached to the lower chip. If the upper and lower chips are different in type or are sized differently, the chip attaching process for each chip may require specific chip-attaching equipment.
Therefore, a conventional chip stack method includes several chip attaching steps and, as a result of the increased handling necessitated by sequentially attaching a series of chips, may increase the possibility of device failure. Furthermore, if several separate pieces of equipment are used sequentially for attaching the respective chips, additional time is required for moving the substrate from apparatus to apparatus which may increase the likelihood of damage or errors that may be reflected in lowered initial quality and/or reliability.
Various attempts to solve these problems have been disclosed in previous publications including the formation of chip stacks at the wafer level. The individual chip stacks are then separated from the wafer(s) and attached to the substrate as a multi-chip unit. However, one such method involves simultaneously sawing two wafers that are attached back surface-to-back surface. As a result, this method is generally limited to chip stacks when chips formed on the two stacked wafers are of substantially identical size and is not suitable for stacking differently-sized chips.
Other publications have taught methods of forming a chip stack with differently-sized chips. However, these conventional methods include individually separating a first chip from a first wafer and then attaching the first chip to a second chip of a second wafer, so process time is still increased relative to a wafer level process and will tend to be susceptible to many of the same problems associated with mounting a series of individual chips on a substrate. Additionally, the conventional methods may also require forming bumps on chip pads or forming extra chip pads and bumps to compensate for chip size variations and are generally unable to form a stack of more than three chips.